BYPASS_CLK_SRC=REF_CLK_24M
Analog ENET PLL Control Register
| DIV_SELECT | Controls the frequency of the ethernet reference clock |
| POWERDOWN | Powers down the PLL. |
| ENABLE | Enable the ethernet clock output. |
| BYPASS_CLK_SRC | Determines the bypass source. 0 (REF_CLK_24M): Select the 24MHz oscillator as source. 1 (CLK1): Select the CLK1_N / CLK1_P as source. |
| BYPASS | Bypass the PLL. |
| PFD_OFFSET_EN | Enables an offset in the phase frequency detector. |
| ENET_25M_REF_EN | Enable the PLL providing ENET 25 MHz reference clock |
| LOCK | 1 - PLL is currently locked; 0 - PLL is not currently locked. |